eTopus is an innovator and technology leader of high performance, mixed-signal, ultra-high speed semiconductor interconnect solutions.
eTopus designs ultra-high speed mixed-signal semiconductor solutions for high-performance computing and data center applications. Our ultra-high speed SerDes is adopted by global major players to be used in storage, enterprise, and hyperscale data center applications. Our solution is also applicable to the fast-growing 5G and AI applications as well. eTopus was among the first to provide standalone SerDes interconnect solution with a monolithic, highly programmable SerDes for the emerging PAM4 standards. Our innovations in ADC/DSP-based physical layer transceiver technology deliver superior performance for Long Reach (high insertion loss channel) at low power consumption for next-generation converged Ethernet deployments.
eTopus is a VC-backed startup headquartered in Sunnyvale, California where all innovations and advanced architectures are developed. We have multiple locations in Hong Kong and Taiwan for design and customer support. Our investors include SK Telecom, HK-X, corporate VCs and cross-border funds.
Technology and Products
eTopus has built from the ground up an advanced system architecture to deliver superior Bit Error Rate (BER) performance for Long Reach (high insertion loss channel) applications. The advanced architecture developed is called eTopus Partial-Response Technology (ePRTTM) architecture. It is a highly programmable and adaptive Receiver DSP architecture, which is fully compatible with existing standards. This innovative architecture is proven with multiple generations of silicon and was tested extensively and collaboratively with our lead customers for performance, robustness, standard compliance and interoperability.
This ePRT approach delivers superior Bit Error Rate thanks to:
Low complexity FFE/DFE optimization engine for perfect equalization signals with ISI
Robust timing recovery, lock to signal even at high Bit Error Rate environment
At the same time, the power scalable design can adjust ADC resolution and levels of Receive Equalization to minimize power consumption at lower insertion loss channel.
The Company product family is called ePhy
The Company product family is called ePhy. The ePhy product line offers an industry first monolithic 200G PAM4 IC, consisting of multiple 50Gbps PAM4 cores and ePRT digital processing technology. ePhy is featured with a 5-tap FIR for transmitting de-emphasis and a non-linear compensation to mitigate non-linear effects. ePhy can transmit and receive channels to scale across multiple data rates addressing 50/100/200/400 GbE product requirements.
Summary of ePhy's Key Features:
• 4 or 8 Full-duplex channels supporting1-28Gbaud PAM4 / NRZ electrical interfaces
• Multi-rate support from 1Gbps to 56Gbps
• The family of PHYs for 50/100/200/400 Gbps interconnects over DAC cables and copper backplanes, and optical fibers.
• ePRT(TM) advanced, highly configurable DSP-based receiver architecture enabling 35dB channel insertion loss performance
• 5-tap FIR for Transmit De-emphasis
• Transmit non-linear compensator to mitigate non-linear effects from optical components
• Full suite of diagnostics including multiple loopback modes, self-test, and on-chip PRBS and checker
• eZEYE(TM) receiver monitor provides mean squared error of link margin for performance analysis and stress testing
• eZLINK(TM) adaptive calibration engine that rapidly converges to the optimal performance under any channel condition
• An evaluation kit, complete with eval board, GUI, documentation, and routines for data analytics
Do you love turning challenges into opportunities? Do you enjoy solving complex problems to support the latest technology innovation? If you are an expert in your field, you are invited to apply for one of the following positions: